Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. Smaller devices can operate at higher speeds since the physical distance between components is smaller. In addition, higher conductivity materials, such as copper, are replacing lower conductivity materials, such as aluminum. One other challenge is to increase the mobility of semiconductor carriers such as electrons and holes.
One technique to improve transistor performance is to strain (i.e., distort) the semiconductor crystal lattice near the charge-carrier channel region. Transistors built on strained silicon, for example, have greater charge-carrier mobility than those fabricated using conventional substrates. One technique to strain silicon is to provide a layer of germanium or silicon germanium. A thin layer of silicon may be grown over the germanium-containing layer. Since the germanium crystal lattice is larger than silicon, the germanium-containing layer creates a lattice mismatch stress in adjacent layers. Strained channel transistors may then be formed in the strained silicon layer.
Another technique is to provide a stress layer over the transistor. Variants of stress layers can be used for mobility and performance boost of devices. For example, stress can be provided by a contact etch stop layer (CESL), otherwise known as a stressed CA liner, stress memory transfer layers, and STI liners. The CA liners can be continuous over the wafer (single CA liner). For both pMOS and nMOS improvement, however, one would need a different CA liner for each (dual stressed CA liner). Most of these techniques use nitride layers to provide tensile and compressive stresses; however, other materials can be used in other applications, e.g., HDP oxide layers.
Another method for inducing strain into the transistor utilizes a modified shallow trench isolation (STI) region. One method includes lining an STI recess with a stressor before filling the recess with a dielectric. The stressor can then impart a stress onto the adjacent semiconductor.
In the field of small, densely packed applications using small geometry CMOS transistors, however, the use of stressed CA liners in the STI region becomes challenging because the smaller the area that can be devoted to the CA liner, the less effective the liner is at delivering a sufficient amount of channel stress.